1. Field of the Invention
The present invention relates to a device for a burst-mode optical clock recovery, and more particularly, to a new device for a burst-mode optical clock recovery which is a core technology in configuring an optical network.
2. Background of the Related Art
As Internet is commonly used and dependence on information and communication is increased in daily lives, service bandwidth requested is accordingly increased. Keeping pace with a Fiber To The Home strategy which requires provision of optical fiber cables to homes at a speed of at least 155 Mbps for the future, the developed countries worldwide are now under study and research. They consider a PON (Passive Optical Network) as the most practical method.
As shown in FIG. 1, the PON comprises an OLT (Optical Line Termination), an ODN (Optical Distribution Network), and an ONU (Optical Network Unit). Here, a device for recovering a burst-mode optical clock is disposed on the OLT.
Data downward to the ONU from the OLT are sent based on a TDM (Time Division Multiplexing) technology. That is to say, there are N number of time slots for information transfer. All the information is transferred to all the n number of subscribers. Each subscriber receives the information by connecting only a time slot assigned to the subscriber.
Meanwhile, data transfer from the ONU to the OLT is performed by a ranging protocol in which a time producing data is adjusted at each subscriber and data are located on a certain time slot as shown in FIG. 1. At this time, optical signals received from the OLT are different in size and phase according to each subscriber. A burst-mode optical receiving module located on the OLT converts the optical signals into electrical signals, makes signal levels constant, and instantly extracts a clock in accordance with the each slot data.
The burst-mode optical signal receiving technology is a general and universal technology applicable to any data communication addressing packet signals. Accordingly, its application range is very large.
At least two clock recovery techniques are currently known.
The first is a method using a high-speed logic gate and a feedback circuit, and the second is a method extracting a clock most close to an input signal after producing multiple clocks having different phases.
The first is representatively taught by U.S. Pat. No. 4,604,756 of Moustakas and by the method using two gated oscillators published by Lucent Technology (IEEE Journal of Lightwave Technology, Vol. 12, pp. 325-331, 1994).
The second is representatively taught by the method for extracting a clock most close to an input data among multiple clocks having different phases, which was published by Alcatel (IEEE Journal of Lightwave Technology, Vol. 12, pp. 271-279, 1994).
The method for burst-mode clock recovery published by Alcatel is so complicated and unsuitable for high-speed operation when being compared with the method disclosed in the U.S. Pat. No. 4,604,756. Therefore, the present invention is based on the method disclosed in the U.S. Pat. No. 4,604,756. However, the present invention improves the method and performs the burst-mode clock recovery in a more stable and reliable manner. Initially, the method disclosed in the U.S. Pat. No. 4,604,756 will be described in detail with reference to FIG. 2.
Referring to FIG. 2, a clock recovering system includes a T/2 delay unit 1, an XOR gate 2, an NOT gate 3, an OR gate 4, a monostable multivibrator 5, and a T delay unit 6.
FIG. 3 shows a timing diagram for explaining the method of FIG. 2.
When a time period of every bit is T, if an arbitrary data is inputted as illustrated in FIG. 3, the data is divided into a signal e1 and the other signal e2. The signal e1 is fed into the XOR gate 2 without any delay while the signal e2 is fed into the XOR gate 2 after passing through the T/2 delay unit 1.
As a result, a signal e3 is generated as illustrated in FIG. 3. Here, let s disregard a gate propagation time and a line propagation time but consider only the delay units 1 and 6.
The electrical signal e3 passes through the inverter 3 and a waveform of the electrical signal e3 is inverted. An output signal e4 is fed into the AND gate 4. At that point, supposing that a feedback signal e6 which is another input of the AND gate 4 is initially a level 1 (in T1), an output e7 of the AND gate 4 passes through the monostable multivibrator 5 and is output as a signal e5.
The monostable multivibrator 5 detects a falling edge of the output signal of the AND gate 4, is synchronized at the edge, produce a level 0 for a time of T/2, increments to the level 1 again and generates the signal e5.
The signal e5 in T1 passes through the T delay unit which is located in a feedback loop and is fed as the input signal e6 of the AND gate 4 again.
Thus, because of the feedback signal, clocks can be output in such sections as T5, T6, etc., which have no input data. However, in case that a time of the T delay unit within the feedback loop is smaller than the input data period T, the system disadvantageously suffers an extreme instability. This will be also explained in FIG. 4.
When a time of the delay unit within the feedback loop is Tf, if the Tf is slightly larger than T, there occurs a synchronization at a falling edge of the signal e4 generated by the input data and the signal e7 is generated as drawn in FIG. 4A, whereby clocks can be stably produced. That is to say, since operation is carried out according to the AND result of the signals e4 and e6, in case of FIG. 4A, a synchronization is enabled at the falling edge of the signal e4 and the monostable multivibrator sends an output. Accordingly, a falling edge of the signal e6 appearing ε time later does not have any effect. However, when the Tf is slightly smaller than T as shown in FIG. 4B, there occurs a synchronization at the falling edge of the fed back signal e6 and the signal e7 is output. If the signal is fed back again, a clock appears on a location of T-2ε. Consequently, if the feedback is repeated, the output signal e7 makes the level section 0 getting wide and the level section 1 getting narrow, resulting in output of the only level 0. That is, only the 0 level signal which is not related the input data is generated and no clocks are generated.
The aforesaid method seems to have little problem in being used for a low-speed burst-mode data clock recovery. If the speed of the input data is increased, however, even though it is fixed that Tf=T+ε(ε>0) at the initial stage, the value of Tf is varied according to various factors including temperature and others, leading to instability in the clock recovery circuit.